This invention relates generally to the field of information storage, and more particularly to a method and apparatus for increasing the bandwidth of a differential amplifier for a disk drive read head.
In general, mass storage devices, such as hard disk drives, include a magnetic storage media, such as rotating disks or platters, a spindle motor, read/write heads, an actuator, a pre-amplifier, a read channel, a write channel, a servo circuit, and control circuitry to control the operation of the hard disk drive and to properly interface the hard disk drive to a host system or bus.
FIG. 1 provides one example of a prior art disk drive mass storage system 30. Disk drive system 30 interfaces and exchanges data with a host 32 during read and write operations. Disk drive system 30 includes a disk/head assembly 12, a preamplifier 14, a synchronously sampled data (SSD) channel 10, and a control circuit 11. Disk/head assembly 12 and preamplifier 14 are used to magnetically store data. SSD channel 10 and control circuitry 11 are used to process data that is being read from and written to disk/head assembly 12 and to control the various operations of disk drive mass storage system 30. Host 32 exchanges digital data with control circuitry 11.
Disk/head assembly 12 includes a number of rotating platters used to store data that is represented as magnetic transitions on the magnetic platters. Read/write heads 13 of disk/head assembly 12 are used to store and retrieve data from each side of the magnetic platters. Read/write heads 13 may comprise any type of available read/write heads such as magneto-resistive heads. Preamplifier 14 serves as an interface between read/write heads 13 of disk/head assembly 12 and SSD channel 10, and provides amplification to the waveform data signals as needed.
SSD channel 10 is used during read and write operations to exchange analog data signals with disk/head assembly 12 through preamplifier 14 and to exchange digital data signals with control circuitry 11 through a data/parameter path 15. SSD channel 10 includes a write channel 16, a read channel 18, a servo control 20, and a parameter memory 22. SSD channel 10 may be implemented as a single integrated circuit.
Some of the various circuit modules of read channel 18 may receive operational parameters for enhanced or optimal performance. The operational parameters are generally calculated during burn-in but may be calculated at other times. The operational parameters are designed to account for the various physical and magnetic characteristics of disk drive mass storage system 30 that vary from system to system and influence operational performance. During start-up, the operational parameters are provided to SSD channel 10 from control circuitry 11 through data/parameter path 15. Parameter memory 22 stores the operational parameters. The various circuit modules of read channel 18 may then access the operational parameters from parameter memory 22 during read operations.
Control circuitry 11 controls the various operations of disk drive mass storage system 30 and to exchange digital data with SSD channel 10, the pre-amp 14 and host 32. Control circuitry 11 includes a microprocessor 28, a disk control 24, a random access memory (RAM) 26, and a read only memory (ROM) 29. Microprocessor 28, disk control 24, RAM 26, and ROM 29 together provide control and logic functions to disk drive mass storage system 30 so that data may be received from host 32, stored, and later retrieved and provided back to host 32. ROM 29 includes preloaded microprocessor instructions for use by microprocessor 28 in operating and controlling disk drive mass storage system 30. ROM 29 may also include the operational parameters, discussed above, that are supplied to parameter memory 22 during start-up. RAM 26 is used for storing digital data received from host 32 before being supplied to SSD channel 10 and received from SSD channel 10 before being supplied to host 32. RAM 26 may also provide data to microprocessor 28 and store data or results calculated by microprocessor 28. Disk control 24 includes various logic and bus arbitration circuitry used in properly interfacing disk drive mass storage system 30 to host 32 and for internally interfacing control circuitry 11 to SSD channel 10 and to the pre-amp status register in pre-amp 14. Depending on the circuit implementation, any of a variety of circuitry may be used in disk control 24.
In operation, disk drive mass storage system 30 goes through an initialization or start-up routine when power is initially provided. One such routine instructs microprocessor 28 to supply operational parameters, previously stored in ROM 29, to parameter memory 22 of SSD channel 10 through data/parameter path 15. The operational parameters are then stored in memory registers of parameter memory 22 for use by read channel 18 during a read operation. Operational parameters may also be stored in the pre-amp status register in pre-amp 14 using bus 15b. 
During read operations, read channel 18 receives analog data signals from read/write heads 13 of disk/head assembly 12 through preamplifier 14. Read channel 18 conditions, decodes, and formats the analog data signal and provides a digital data signal in parallel format to control circuitry 11 through data/parameter path 15. Read channel 18 includes any of a variety of circuit modules such as an automatic gain control circuit, a low pass filter, a variable frequency oscillator, a sampler, an equalizer, such as a finite impulse response filter, a maximum likelihood, partial response detector, a deserializer, and a synchronization field detection circuit. Read channel 18 provides the digital data signal to disk control 24 through data/parameter path 15. Disk control 24 provides various digital logic control and arbitration circuitry between SSD channel 10, host 32, RAM 26, microprocessor 28, and ROM 29 during both read and write operations.
The bandwidth of the system is typically limited by the lead inductance associated with the magneto-resistive read/write head. The limited bandwidth is attributable to a pole caused by the combination of the resistance and lead inductance of the magneto-resistive read/write head, which causes a roll off in the system""s frequency response.
One approach to increasing the bandwidth of a hard disk drive is to introduce a zero at a frequency corresponding to the pole due to the lead inductance of the magneto-resistive element. One method of locating such a compensating zero was introduced in a prior application, U.S. application Ser. No. 09/211,938 filed Dec. 15, 1998 by Bernard R. Gregoire et. al. In that application, an adjustable impedance boosting circuit was described that improved over the prior techniques by providing an adjustable compensating zero. That invention had several important technical advantages. Varying the impedance of the variable impedance load in proportion to the actual value of the magneto-resistive element facilitates adjustable compensation for a pole caused by the lead inductance of the magneto-resistive element. This prior invention provided a method and apparatus for approximating a compensating zero that is responsive to variations in the actual value of the magneto-resistive element. The peak-limiting circuit prevents peaks in the frequency response by rolling off the gain of the variable impedance load at a selected frequency.
While the previously described prior invention provided an adjustable impedance boosting circuit that adjusted a compensating zero for variations in the actual value of the magneto-resistive element for a given head, it is desirable to put the impedance boosting circuit in subsequent gain stages. Further, it is desirable to adjust the response of the impedance boosting circuit in a subsequent stage. Adjusting the impedance response is needed to allow further bandwidth improvement despite variations in the head resistance. Also, adjustment of the impedance boosting circuit through the status register allows optimization of the boosting circuit and compensation for variations in the lead inductance values which may vary drive to drive as well as compensating for process variations after chip fabrication.
A selectively adjustable impedance boosting circuit for a magneto-resistive head in a disk drive is introduced in the present invention to compensate a frequency pole by introducing a zero in proportion to the resistance of the magneto-resistive element and with selectable circuit parameters to further adjust the pole compensation. Embodiments of the present invention include selectively adjusting one or more of the following parameters: the sensitivity of the pole compensation to changes in the resistance of the head, the peak compensation, and the frequency of the compensating zero.